A power metal-oxide-semiconductor field-effect transistor (MOSFET) is a type of MOSFET that is adapted for use in high power applications. Generally, a power MOSFET has a vertical structure, wherein a source and gate contact are located on a top surface of the body of the MOSFET, and the drain contact is located on a bottom surface of the body of the MOSFET. These “vertical” MOSFETs are sometimes referred to as vertical diffused MOSFETs (VDMOSFETs) or double-diffused MOSFETs (DMOSFETs).
A conventional vertical MOSFET generally includes a substrate and a drift layer formed over the substrate. One or more junction implants extend into the drift layer from the top surface of the drift layer. A junction gate field effect transistor (JFET) region is provided between the junction implants. Each one of the junction implants is formed by an ion implantation process and will include at least a source region. Each source region is formed in a shallow portion beneath the top surface of the drift layer. A gate dielectric is formed along the top surface of the drift layer and extends laterally between each source region. A gate contact is formed over the gate dielectric. Source contacts are formed over source regions, and a drain contact is formed on the bottom surface of the substrate.
The long term reliability of the vertical MOSFET is often a function of the quality of the interface between the JFET region and the gate dielectric. Further, this interface dictates the MOSFET's gate-to-drain capacitance, which directly affects switching speeds; gate leakage currents in both the on and off states; and blocking voltages in the off state. Since there is always a need to improve device reliability, reduce gate-to-drain capacitance, and reduce leakage currents, there is a need to improve the interface between the JFET region and the gate dielectric in vertical MOSFETs and other field effect devices.